The processor in your phone is not one chip, and stopping making it one is where the last decade's gains came from

Public conversation about chips is almost entirely about one number: the node, quoted in nanometres, treated as a measure of how advanced a processor is. That number stopped being a physical measurement of anything years ago, and — more importantly — it stopped being where most of the improvement comes from. For roughly the last decade, a large share of the gains in real computing hardware has come not from making transistors smaller but from abandoning the idea that a processor should be one piece of silicon.

A big chip is a bad bet on a wafer

Defects land on a silicon wafer roughly at random: a particle, a lithography flaw, a contamination event. Each defect kills whatever die it lands in.

That gives die size a punishing arithmetic. If you cut a wafer into many small dies, a defect destroys a small one and the rest survive. Cut the same wafer into a few very large dies and each defect destroys a much bigger share of your output. Yield does not decline gently with area — it falls away steeply, and for large dies at a new process node it can be the difference between a viable product and an unsellable one.

There is also a hard ceiling. Lithography prints through a mask onto a limited field, and that reticle limit — somewhere around 800 square millimetres — is the largest single die that can be exposed in one shot. You cannot simply draw a bigger chip.

And a third problem, less obvious and increasingly decisive: not every circuit benefits from the newest node. Logic still shrinks usefully. SRAM, the memory built into processors, has scaled far more slowly in recent generations. Analog circuits, power delivery and input/output interfaces barely scale at all — they are governed by physics that does not care about transistor length. Building all of that on the most expensive silicon available means paying leading-edge prices per square millimetre for functions that gain nothing from it.

Build it out of pieces instead

The response is to stop making one chip. A modern processor is often several chiplets — separate dies, each fabricated on the process node that suits its job, assembled into a single package that behaves like one component.

The compute cores go on the newest, most expensive node, where they actually gain. The input/output, memory controllers and analog blocks go on an older, cheaper, thoroughly debugged node where they perform just as well. Cache can be its own die. Yield improves because each die is small. Product planning improves too, because a manufacturer can combine different numbers of the same compute die to make a whole product line instead of designing and validating a separate chip for each tier.

This is not a compromise forced by failure. It is a recognition that "one chip" was always an arbitrary constraint inherited from an era when everything scaled together.

Why the connection between the pieces is the entire problem

Splitting a processor is easy. Making the pieces talk without losing everything you gained is the hard part, and the reason is energy.

Moving data costs energy in proportion to how far it travels and what it has to drive. On a single die, wires are short and thin and the energy per bit is very small. Push that same bit off the die, through a package, across a circuit board, and the cost rises by orders of magnitude — to the point where in modern hardware, transporting an operand can cost more energy than the arithmetic performed on it. A chiplet design that communicates like a traditional multi-chip board would give back more than it gained.

So the packaging had to become as sophisticated as the lithography. 2.5D integration places the dies side by side on a silicon interposer — effectively a piece of silicon used as wiring, carrying connections finer than any circuit board can achieve, so the dies communicate over short, dense, low-energy links. 3D integration goes further and stacks dies vertically, connecting them with through-silicon vias: holes etched right through a wafer and filled with metal, so signals pass through the body of the silicon rather than around it. The newest approach, hybrid bonding, dispenses with solder bumps entirely and joins two dies by direct copper-to-copper contact across their polished faces, which shrinks the connection pitch by roughly an order of magnitude and shortens the wires further still.

The number worth watching is not transistors per square millimetre. It is picojoules per bit moved — and every advance in packaging is an attack on that number.

Stacked memory, and why AI hardware is packaging-limited

This is where it stops being an abstraction. Machine learning accelerators are constrained by memory bandwidth: generating text one token at a time means reading a model's weights out of memory continuously, and the processor spends much of its life waiting.

The answer in current hardware is stacked memory — DRAM dies bonded on top of one another with through-silicon vias and placed immediately beside the processor on an interposer. Because the connection is short and made through silicon rather than a board, it can be enormously wide: thousands of parallel connections instead of the few dozen a conventional memory bus manages. Bandwidth rises by roughly the width of the bus.

The consequence is worth stating plainly, because it inverts the usual story. The supply constraint on AI accelerators has often been advanced packaging and stacked memory capacity rather than lithography. The bottleneck moved from printing transistors to assembling them.

What gets harder

Nothing here is free, and the new difficulties are mechanical rather than electronic.

Heat. Stacking puts a die between a heat source and the heatsink. A hot layer buried in the middle of a stack has no direct path out, which constrains how much power each layer may dissipate and shapes what can physically be stacked on what.

Mechanical stress. Silicon, copper, organic substrate and solder all expand at different rates when heated. Bond several of them into a rigid assembly, cycle it through temperature, and you get warpage and fatigue at exactly the fine connections you worked so hard to make.

Known-good-die testing. This one is subtle and expensive. If you assemble eight dies into a package and one is faulty, you have not lost one die — you have lost the package and the seven good dies with it. So every die must be thoroughly tested before assembly, which is difficult when its interfaces were designed to be probed only after bonding. Test cost rises sharply, and it is a real constraint on how many chiplets a design can afford to combine.

Interfaces. For chiplets from different companies to interoperate, the link between them needs to be standardised, which is what industry efforts such as UCIe are attempting. An open chiplet marketplace would change the economics of chip design considerably, and it is not there yet.

Why it matters for students and researchers

Packaging used to be the industry's back end — the unglamorous assembly and test step performed after the interesting work was finished, usually somewhere else and usually for less money. It is now where a large part of system performance is determined, and the skills are correspondingly different from front-end design: thermomechanical simulation, materials selection, high-frequency signal integrity, metrology and test engineering.

For India this is not an abstract observation. Most of the projects approved under the country's semiconductor programme are assembly, test and packaging plants rather than leading-edge fabs, with fab capacity following behind. That has sometimes been described as settling for the low-value end of the industry. On the technical merits, that description is out of date: advanced packaging is where a meaningful share of current performance gains are being extracted, and it is the part of the supply chain that has repeatedly been the binding constraint on AI hardware. Anyone entering electronics or materials engineering in India is entering an industry whose growth is happening precisely in this layer — and the interesting problems there are thermal, mechanical and metrological rather than lithographic.

Frequently asked questions

What is a chiplet?

It is one of several separate silicon dies assembled into a single processor package, each made on the process node best suited to its function, connected so that the package behaves as one component.

Why not just make one large chip?

Because manufacturing defects fall roughly at random across a wafer, so yield drops steeply as die size grows, and lithography cannot expose a die larger than the reticle limit of roughly 800 square millimetres. Large single dies are also wasteful when parts of the circuit gain nothing from an advanced node.

Why does packaging affect performance so much?

Because moving data between dies costs energy and time, and in modern hardware transporting a value can cost more energy than computing with it. Interposers, through-silicon vias and hybrid bonding shorten those connections and make them denser, which is what preserves the benefit of splitting a chip.

What is stacked memory and why does AI hardware need it?

It is DRAM dies bonded vertically with through-silicon vias and placed beside the processor, giving a very wide, short connection. AI accelerators are limited by how fast weights can be read from memory, so bandwidth rather than raw arithmetic often determines their speed.

What is the known-good-die problem?

If a package contains several dies and one is defective, the entire assembly is scrapped along with the working dies in it. Each die must therefore be tested thoroughly before assembly, which is technically awkward and adds significant cost.